By Ricardo Lourenço, Nuno Lourenço, Nuno Horta
This paintings addresses the study and improvement of an cutting edge optimization kernel utilized to analog built-in circuit (IC) layout. relatively, this works describes the alterations contained in the AIDA Framework, an digital layout automation framework absolutely built via on the built-in Circuits Group-LX of the Instituto de Telecomunicações, Lisbon. It focusses on AIDA-CMK, by way of bettering AIDA-C, that's the circuit optimizer component to AIDA, with a brand new multi-objective multi-constraint optimization module that constructs a base for a number of set of rules implementations. The proposed resolution implements 3 methods to multi-objective multi-constraint optimization, specifically, an evolutionary procedure with NSGAII, a swarm intelligence procedure with MOPSO and stochastic hill mountaineering strategy with MOSA. additionally, the applied constitution permits the straightforward hybridization among kernels reworking the former easy NSGAII optimization module right into a extra developed and flexible module helping a number of unmarried and multi-kernel algorithms. the 3 multi-objective optimization ways have been verified with CEC2009 benchmarks to restricted multi-objective optimization and established with genuine analog IC layout difficulties. The completed effects have been in comparison when it comes to functionality, utilizing statistical effects got from a number of autonomous runs. ultimately, a few hybrid methods have been additionally experimented, giving a foretaste to quite a lot of possibilities to discover in destiny work.
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Extra resources for AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing
One such technique is PVT corner simulations. , that lead to the worst-case performance. 5 illustrates eight corner cases obtained by considering three values for power supply, operating temperature, and process parameters. , for each evaluation, the circuit is simulated once for each corner case, this makes the execution slower when compared to typical, but the output circuits are ensured to be feasible in all tested corner conditions. 3), where, C is the number of corners, and fmc ð xÞ and gcj ð xÞ are respectively the 22 3 AIDA-CMK: AIDA-C with MOO Framework Fig.
3. The analysis of the obtained fronts shows a notorious degradation of the MOPSO performance, when dealing with problems of larger dimension. The degradation in CF1 and CF2 is not that large, but is notorious for the other problems (CF3–CF7). Regarding both MOSA and NSGAII the performance looks similar in Fig. 3. However, if the MOSPO is removed, a closer look shows that the implemented MOSA greatly outperforms the NSGA-II in CF3–CF7, as illustrated in Fig. 4. 3 Evaluation of the Multi-kernel Methods 45 Fig.
Also, it can be observed that the best between shuffle and sort by objective is dependent on the problem, where in CF1, CF2, and CF3 the shuffle method is better and in CF5, CF6, and CF7 the sort by objective tends to be better. To evaluate the performance of the multi-kernel algorithms four combinations of two kernels were tested. 2. In Fig. 6 the results obtained for the four multi-kernel combinations are presented. 46 5 Kernel Validation Using CEC2009 Benchmarks Fig. 3 Pareto fronts for problems with 30 variables: CF1–CF7 Fig.
AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing by Ricardo Lourenço, Nuno Lourenço, Nuno Horta